SERDES slices for platform Asic

LSI Logic has added to its RapidChip structured Asic family new design options for high speed serial applications.

Available are up to 48 SERDES (serialiser/deserialiser) elements, up to five million gates and 3.7Mbits of RAM, based on the firm’s recently introduced MatrixRAM internal memory architecture. There is also support for high bandwidth memory interfaces such as DDR2 and QDR.

Called the Xtreme2 family, it offers various SERDES combinations under the GigaBlaze and Hydra names. With data rates up to 4.25Gbit/s, supported standards include, but are not limited to, Gigabit Ethernet, 10 Gigabit Ethernet (XAUI), PCI Express (including ASI), Fibre Channel, InfiniBand, CX4, Serial Rapid IO, SGMII, SPI4.2, SPI5, SAS, SATA, and HyperTransport standards.

The MatrixRAM architecture consists of memory arrays which can be used individually or combined to form larger memories configured in different widths and depths.

Supported memory standards include DDR2, which is emerging as the dominant memory technology in enterprise computing; RLDRAM2 and FCRAM2 common in high performance networking and QDR common in storage networking.

Fast LVDS buses like SPI-4.2 can be implemented in Configurable I/O.

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