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First PWM controller with AVSBus, supplies up to 450A for FPGAs

Intersil ISL68137

There are 12 controllers, providing up to seven phases which can be shared-out between two output voltage rails in any combination. The firm has also created an output power-switching chip (see below) to be used one-per-phase, allowing supplies from 10A to 450A to be created.

The controllers come in three groups:

Intersil ISL68137 syn current loopAll of them have a digital engine with a patented synthetic current control architecture that tracks each phase current with zero latency, said the firm. “This allows the device to respond to any load transient with precise current and voltage positioning, and 30% less capacitance than competitive devices.” – allowing all-ceramic capacitor designs for high-reliability PSUs.


There are also all compliant to both PMBus 1.3 and AVSBus, have cycle-by-cycle current protection (average and peak thresholds) and include autonomous auto phase dropping.

Input and output both have over-voltage and under-voltage protection and telemetry for both voltage and current, and there is temperature fault reporting.

Intersil ISL68137 plus drivers, with AVSBusSmart power stage

The associated power stage is the ISL99227 which is rated at 60A and will operate with inputs from 4.5 to 18V. Internal synchronous FETs are rated at 25V.

It includes current sensing with 3% accuracy across line, load and temperature, plus differential current reporting at 5mV/A and temperature sensing.

The high-side FET is over-current protected, and it comes in a 5 x 5mm, 32 lead QFN.

14 phases

An existing chip, the ISL6617A, can be used to double a phase, so seven of these can be added to create a 14 phase PWM controller.

A development tool, PowerNavigator, connects to development boards through PMBus and AVSBus to set parameters including the current thresholds for adding/dropping phases and loop tuning. The final configuration is simply stored to non-volatile memory.

AVSBus

AVSBus is specified by the PMBus organisation and is intended to save power without compromising processing performance by allowing the processor (CPU, FPGA, SoC or asic) to command a cut in supply voltage immediately prior to entering low-power modes like hibernation or sleep, and increases in voltage when fast processing is required.

Intersil has created some videos to go along with these power chips.